In synchronizing signal outputs, it has been found desirable to clock different logic states on different clocks. A certain signal may be a logic high or a logic low, but is to be received only at certain predetermined times. When that predetermined time is may actually depend on what the logic state of the signal is. For example, it may be desirable to receive the signal on a first clock if the signal is a logic high, but on a second signal if the signal is a logic low. U.S. Pat. No. 4,379,241, Pumo, teaches an edge defined output buffer for achieving this result. In designing a large scale integrated circuit, there may be numerous such situations in which signals are to be clocked but at different times depending on the logic state. Some such signals may have the logic high clocked on a first clock, and the logic low on a second clock. Whereas, other such signals would have the low clocked on the first clock, and the logic high clocked on the second clock. Furthermore, in the course of design, changes may be made as to when such logic states are clocked. These changes may in fact occur relatively late in the design. Such changes can cause costly delays, particularly in laying out the integrated circuit.